1. Field of the Invention
The present invention relates to a power supply circuit having a current mirror.
2. Description of the Related Art
As a circuit for producing a reference power supply voltage, a bandgap power supply circuit having a current mirror circuit has been used (see Japanese Patent Application Laid-open 2001-202147, for example).
FIG. 1 is a schematic circuit diagram showing a configuration of a conventional bandgap power supply circuit. Referring to FIG. 1, a conventional bandgap power supply circuit includes transistors MP1 to MP3, transistors MN1 and MN2 and transistors B1 to B3 and resistances R1 and R2.
For calculation simplicity, it is assumed that transistors MP1 to MP3 are PMOS transistors of an identical size; transistors MN1 and MN2 are NMOS transistors of an identical size; transistors B1 to B3 are PNP bipolar transistors; transistor B1 and transistor B3 have an identical emitter size; and transistor B2 has an emitter size greater than transistor B1.
Transistor MP1, transistor MN1 and transistor B1 are connected in series in this order to power supply Vcc. Similarly, transistor MP2, transistor MN2, resistance R1 and transistor B2 are connected in series in this order to power supply Vcc. Further, transistor MP3, resistance R2 and transistor B3 are connected in series in this order from power supply Vcc. Transistors MP1 to MP3 constitute a current mirror portion. Output voltage BGREF is output from the node between transistor MP3 and resistance R2.
Here, currents flowing through transistors MP1, MP2 and MP3 will be denoted as I1, I2 and I3, respectively. The potential difference between both ends of resistance R1 will be denoted as ΔVBE.
Resistances R1 and R2 are set up with appropriate values so that the temperature dependence of BGREF is minimized.
Further, the base-emitter voltages of transistors B1, B2 and B3 are referred to as VBE1, VBE2 and VBE, respectively.
The conventional bandgap power supply circuit having the above configuration produces a reference power supply voltage as an output voltage when power supply Vcc is given. This output voltage BGREF is represented as Eq.(1)BGREF=VBE+R2·I3  (1)
On the other hand, potential difference ΔVBE between both ends of resistance R1 is represented by Eq.(2) and current I3 flowing through transistor MP3 is represented by Eq. (3).ΔVBE=R1·I2  (2)I3=I2  (3)
Eq. (4) is obtained from Eq.(2) and Eq. (3).I3=ΔVBE/R1  (4)
Substituting Eq. (1) into this Eq. (4) gives Eq.(5).BGREF=VBE+(R2/R1)·ΔVBE  (5)
Here, if it is assumed that there is no variation in PMOS transistor characteristics and threshold voltage Vth of transistor MP2 has no offset relative to that of transistor MP1, currents I2 and I1 flowing through transistor MP1 and transistor MP2 are equal to each other, as shown in Eq. (6).I2=I1  (6)
Further, if Eq. (7) is true and when the emitter area of transistor B1 and the emitter area of transistor B2 are denoted by A1 and A2, respectively, then Eq. (8) holds, where q is the elementary charge, k is the Boltzmann constant, T is the absolute temperature of the PN junction.
                              Δ          ⁢                                          ⁢          VBE                =                              VBE            ⁢                                                  ⁢            1                    -                      VBE            ⁢                                                  ⁢            2                                              (        7        )                                          I          ⁢                                          ⁢                      1            /            I                    ⁢                                          ⁢          2                =                              A            ⁢                                                  ⁢            1            ⁢            exp            ⁢                                                  ⁢                          (                                                q                  ·                  VBE                                ⁢                                                                  ⁢                                  1                  /                  kT                                            )                                            A            ⁢                                                  ⁢            2            ⁢            exp            ⁢                                                  ⁢                          (                                                q                  ·                  VBE                                ⁢                                                                  ⁢                                  2                  /                  kT                                            )                                                          (        8        )            
Eq. (8) can be transformed into Eq. (9).VBE1−VBE2=kT/q·ln((I1/I2)·(A2/A1))  (9)Substituting Eq. (6) and Eq. (7) in Eq. (9) produces Eq. (10).ΔVBE=kT/q·ln(A2/A1)  (10)
From Eq. (5) and Eq. (10), output voltage BGREF can be represented asBGREF=VBE+(R2/R1)·(kT/q)·ln(A2/A1)  (11)
It is understood that VBE has a negative temperature dependence, but the temperature dependence can be cancelled out by adjusting R2/R1.
However, the prior art technology described above entails the problem as follows.
The above description was made referring to a case where threshold voltage Vth of transistor MP2 has no offset, but there are cases where some offset occurs due to variation in PMOS transistor characteristics. As a result, a shift of the output voltage from the bandgap power supply circuit takes place.
To begin with, threshold voltage Vth of transistor MP2 is presumed to have an offset of ΔVp relative to that of transistor MP1. When the threshold voltage Vth of transistor MP1 is denoted by Vp, threshold voltage Vth of transistor MP2 is given as Vp+ΔVp.
Here, when the S-parameter involving transistors MP1 and MP2 is read as S, aforementioned Eq. (6) does not hold, and the relationship between currents I2′ and I1′ flowing through transistors MP1 and MP2 can be given by Eq. (6′) instead.I2′=I1′·10(−ΔVp/S)  (6′)
Accordingly, the aforementioned Eq. (10) is rewritten as Eq. (10′).ΔVBE′=(kT/q)·{(ΔVp/S)·ln 10+ln(A2/A1)}  (10′)
According to Eq. (5), a shift ΔBGREF (=BGREF′−BGREF) arising in output voltage BGREF is given by Eq. (12).ΔBGREF=(R2/R1)·(ΔVBE′−ΔVBE)  (12)
By inserting Eq. (10) and Eq. (10′) into Eq. (12), Eq. (13) is obtained.ΔBGREF=(R2/R1)·(kT/q)·ln 10·(ΔVp/S)  (13)
Here, as a specific example where it is assumed that R2/R1=8, T=27 deg. C., S=90 mV/K are assumed, output voltage shift ΔBGREF is given asΔBGREF=5.32·ΔVp  (13′)which is understood to be the shift that will occur.
Next, threshold voltage Vth of transistor MP3 is presumed to have an offset of ΔVp relative to that of transistor MP2. When the threshold voltage Vth of transistor MP2 is denoted by Vp, threshold voltage Vth of transistor MP3 is given as Vp+ΔVp.
Here, when the S-parameter involving transistors MP2 and MP3 is read as S, aforementioned Eq. (3) does not hold, and the relationship between currents I3′ and I2′ flowing through transistors MP2 and MP3 can be given by Eq. (3′) instead.I3′=I2′·10(−ΔVp/S)  (3′)
Accordingly, the aforementioned Eq. (4) is rewritten as Eq. (4′).I3′=(1/R1)·10(−ΔVp/S)·ΔVBE  (4′)
By inserting this Eq. (4′) into Eq. (1),BGREF′=VBE+(R2/R1)·10(−ΔVp/S·ΔVBE  (5′)From Eq. (5′) and Eq. (5) the output voltage shift ΔBGREF is
                                                                        Δ                ⁢                                                                  ⁢                BGREF                            =                                                BGREF                  ′                                -                BGREF                                                                                        =                                                                    {                                                                  10                                                  (                                                                                    -                              Δ                                                        ⁢                                                                                                                  ⁢                                                                                          V                                p                                                            /                              S                                                                                )                                                                    -                      1                                        }                                    ·                                      (                                          R                      ⁢                                                                                          ⁢                                              2                        /                        R                                            ⁢                                                                                          ⁢                      1                                        )                                    ·                  Δ                                ⁢                                                                  ⁢                VBE                                                                        (        14        )            
By inserting this Eq. (14) into Eq. (10),ΔBGREF={10(−ΔVp/S)−1}·(R2/R1)·(kT/q)·ln(A2/A1)  (15)
Here, as a specific example where it is assumed that R2/R1=8, A2/A1=8, T=27 deg. C., S=90 mV/K, output voltage shift ΔBGREF is given as
                                                                        Δ                ⁢                                                                  ⁢                BGREF                            =                                                                    {                                                                  10                                                  (                                                                                    -                              Δ                                                        ⁢                                                                                                                  ⁢                                                                                          V                                p                                                            /                              S                                                                                )                                                                    -                      1                                        }                                    ·                  8                  ·                                      (                                          kT                      /                      q                                        )                                    ·                  ln                                ⁢                                                                  ⁢                8                                                                                        =                                                {                                                            10                                              (                                                                              -                            Δ                                                    ⁢                                                                                                          ⁢                                                                                    V                              p                                                        /                            0.09                                                                          )                                                              -                    1                                    }                                ·                0.43                                                                        (                  15          ′                )            which is understood to be the shift that will occur.
Next, threshold voltage Vth of transistor MN2 is presumed to have an offset of ΔVn relative to that of transistor MN1. When the threshold voltage Vth of transistor MN1 is denoted by Vn, threshold voltage Vth of transistor MN2 is given as Vn+ΔVn.
In this case, −ΔVn is added to ΔVBE in the above Eq. (5). Accordingly, the output voltage shift ΔBGREF is given asΔBGREF=−(R2/R1)·ΔVn  (16)
Here, as a specific example where it is assumed that R2/R1=8, output voltage shift ΔBGREF is given asΔBGREF=−8·ΔVn  (16′)which is understood to be the shift that will occur.
FIG. 2 is a graph showing the relationship between the offset of threshold voltage Vth and output voltage shift ΔBGREF in the three specific examples. In FIG. 2, the output voltage shifts ΔBGREF, given by Eq. (13′), Eq. (15′) and Eq. (16′), are plotted by 91, 92 and 93, respectively. It is understood that, as an offset of about 20 mV occurs in threshold voltage Vth, output voltage BGREF will have a shift of about 300 mV max. That is, there is a possibility that an output voltage shift that is equal to ten times of, or greater than, the offset occurring in threshold voltage Vth may take place.
Further, here for calculation simplicity it was assumed that transistors MP1 to MP2, MN1 and MN2 are of an identical size and transistors B1 and B3 are of an identical size. However, in other than the above case a serious shift will similarly take place in output voltage BGREF, due to the influence of threshold voltage Vth.
As described above, in the conventional bandgap power supply circuit, there has been the problem that the output voltage is seriously affected by minute variation in device characteristics.
In the actual LSIs, variation in characteristics will take place due to anisotropy and layout pattern dependence, however, such variation to some extent is regarded to be within tolerance. However, as for the bandgap power supply circuits, it has become difficult to operate the current mirror portion in saturated range as LSIs developed into low-voltage configurations. As a result, some level of minute variation which can be permitted in usual circuits may cause a serious output voltage shift in a bandgap power supply circuit, which cannot be permitted.